Objective-Based Low-Frequency Parasitic Inductance Characterization Method for Power Semiconductor Package With High Power and Switching Speed

Characterizing package parasitic inductance is significant for package design, dynamic characteristic evaluation, thermal management, and insulation breakdown protection. As package parasitic inductances become smaller and the switching speed of the power semiconductor becomes higher, traditional and widely-used double pulse tests based on the “<inline-formula><tex-math notation="LaTeX">$L = V/({di/dt})$</tex-math></inline-formula>” and “<inline-formula><tex-math notation="LaTeX">$L = {\rm{ }}1/({4{\pi }^2{f}^2C})$</tex-math></inline-formula>” present more critical drawbacks in accuracy and adaptability. This letter proposes a novel method called objective-based low-frequency-range parasitic inductance characterization to accurately obtain the parasitic inductance of semiconductor packages. The proposed method directly extracts the package inductances instead of the current commutation loop and can be carried out under low bus voltage and low frequency. Thus, the proposed method features higher robustness, adaptability, and accuracy. Experimental results in the commercial silicon carbide power device/module validate the feasibility and superiority of the proposed method.