A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC

This paper presents a 13-tap FIR filter and an IIR filter embedded in a 10-bit SAR ADC for wireless communications chip. The IIR filter can be inherently realized through reusing the capacitor array of the SAR ADC, thus improving the stopband suppression and shaping the transition band. Besides, the DC attenuation is also avoided. The sampling rate loss of the SAR ADC can be compensated by the <inline-formula> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> time-interleaving technology. The proposed filter features high power-efficient, linearity and process compatibility. Compared with a 15-tap FIR filter, the out-of-band suppression at the cut-off frequency (OOBS@<inline-formula> <tex-math notation="LaTeX">$f_{\mathrm {cut-off}}$ </tex-math></inline-formula>) is enhanced by 9dB theoretically. A prototype FIR/IIR filter in 40nm CMOS occupies an active area of 0.067mm2, consumes <inline-formula> <tex-math notation="LaTeX">$38~\mu \text{W}$ </tex-math></inline-formula> at a single supply of 1.1V, has a 1-MHz bandwidth, obtains <inline-formula> <tex-math notation="LaTeX">$>$ </tex-math></inline-formula>42.2dB OOBS@5.9MHz when operated at 40MS/s. Meanwhile, the SAR ADC without/with the proposed filter can achieve a FoMw of 7.91 fJ/conversion-step and 13.5 fJ/conversion-step, respectively.