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A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
- Source :
- IEEE Journal of Solid-State Circuits; 2023, Vol. 58 Issue: 7 p2075-2086, 12p
- Publication Year :
- 2023
-
Abstract
- A 0.7-pJ/bit, 8.5-Gb/s/link inductive coupling interchip wireless communication interface for a 3D- stacked static-random access memory (SRAM) has been developed in a 7-nm FinFET process. A new physical placement method that allows coils to be placed over off-the-shelf SRAM macros with small magnetic field attenuation, together with the use of synchronous communication using Manchester encoding and a clocked comparator to enable the detection of small-swing signals, achieves a 26% reduction in SRAM die area compared to through-silicon via (TSV)-based stacking. Interchip communication at 0.7 pJ/bit, 8.5 Gb/s/link was confirmed using test chips. A 4-hi 3D- stacked SRAM module using the proposed interface achieves a 1.2-TB/s/mm<superscript>2</superscript> area efficiency, representing a two orders-of-magnitude improvement over the state-of-the-art 3D- stacked SRAM.
Details
- Language :
- English
- ISSN :
- 00189200 and 1558173X
- Volume :
- 58
- Issue :
- 7
- Database :
- Supplemental Index
- Journal :
- IEEE Journal of Solid-State Circuits
- Publication Type :
- Periodical
- Accession number :
- ejs63411172
- Full Text :
- https://doi.org/10.1109/JSSC.2022.3224421