Cryogenic Hysteresis in 110 nm Bulk Silicon MOSFETs for Capacitorless Memory Applications

In this letter, we characterize the commercial 110 nm bulk silicon MOSFETs down to 6 K, with a focus on cryogenic capacitorless memory applications. The substrate-induced steep subthreshold swing (SS) and hysteretic loop are observed at low temperatures. At 6 K with <inline-formula> <tex-math notation="LaTeX">${V}_{\text {D}}$ </tex-math></inline-formula> = 1.8 V, the minimum SS is <inline-formula> <tex-math notation="LaTeX">$\boldsymbol { &lt; }0.3$ </tex-math></inline-formula> mV/dec and the hysteretic loop is <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {>}\, 0.2$ </tex-math></inline-formula> V wide with a <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\sim }10 \boldsymbol {^{{8}}}$ </tex-math></inline-formula> ratio of high to low drain current states. For the first time, we demonstrate the cryogenic capacitorless memory operation of bulk silicon MOSFETs. It shows a <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\sim }12 \boldsymbol {\mu }\text{A}$ </tex-math></inline-formula> sense margin, long retention time (on the scale of minutes when T <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\leq }\, 30$ </tex-math></inline-formula> K), and high write and read endurance. These features make it promising as a compact capacitorless single-transistor memory for low-temperature applications.