Design Automation Framework for Placement and Clock Tree Synthesis of Superconducting Rapid Single-Flux-Quantum Logic

This article presents a design automation framework for the placement and clock tree synthesis of superconducting rapid single-flux-quantum (RSFQ) logic. The framework includes a global placement method for gate-level-pipelined layout optimization, a clock tree synthesis procedure for HL-tree construction with concurrent-flow and counter-flow schemes, and a detailed placement method for congestion optimization. In the global placer, the optimization problem is reformulated to reduce the run-time cost while maintaining optimization quality; the clock tree synthesis is performed using the bottom-top iterative algorithm, combining synchronizer synthesis and clock tree construction to shrink the size of the clock tree; eventually, the detailed placer performs the algorithm based on Delaunay triangulation and Lloyd iteration, adjusting layout placement under certain constraints. Several benchmarks are used to validate the effectiveness of the proposed framework, and the results show that the framework is capable of maximizing the utilization of layout space and providing a routable layout environment for hybrid routing within a controlled run-time.