Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor

This paper proposes a simplified analytical approach to analyze the influence of process variations including quantum confinement effect (QCE) on the functionality of ultralow power (ULP) subthreshold 1) inverter and 2) Schmitt trigger (ST) circuits implemented with gate-all-around (GAA) junctionless (JL) nanowire transistor (NWT). QCE and variability-centric analysis of process corners reveal severe constraints to maintain functionality in worst-case scenarios corresponding to 1) fast NMOS–slow PMOS for inverter as noise margin reduces; 2) slow <inline-formula> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula>-sub-circuit-fast <inline-formula> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula>-sub-circuit in ST as symmetry is disturbed; and 3) slow NMOS and PMOS feedback transistors in ST as hysteresis width is degraded. In addition, the minimum operating voltage is shown to degrade for the above cases i.e. <inline-formula> <tex-math notation="LaTeX">$\sim \times 8$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$\sim \times 3$ </tex-math></inline-formula> higher than the nominal case for ULP inverter and ST, respectively. A ULP circuit implemented using JL devices with moderate doping and longer underlap is the best suited to accommodate <inline-formula> <tex-math notation="LaTeX">$3\sigma $ </tex-math></inline-formula> variations in threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\mathbf {th}}$ </tex-math></inline-formula>). The proposed approach serves as a guide to evaluate and mitigate the impact of the variability in ULP circuits.