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A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications
- Source :
- IEEE Journal of Solid-State Circuits; February 2024, Vol. 59 Issue: 2 p551-562, 12p
- Publication Year :
- 2024
-
Abstract
- This article presents a four-phase time-based switched-capacitor low-dropout (SCLDO) regulator that regulates an output load voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\text {OUT}}$ </tex-math></inline-formula>) of 0.35–0.95 V with an input voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\text {IN}}$ </tex-math></inline-formula>) of 0.45–1 V. The regulator employs a four-phase time quantizer, which enables high proportional gain control and short transient response time with relatively low quiescent current. In addition, the proposed SCLDO employs a 9.6-pF coupling capacitor (<inline-formula> <tex-math notation="LaTeX">$C_{\text {C}}$ </tex-math></inline-formula>) that is connected to the gate voltage of the pass transistor and <inline-formula> <tex-math notation="LaTeX">$V_{\text {OUT}}$ </tex-math></inline-formula> node, thereby reducing the <inline-formula> <tex-math notation="LaTeX">$V_{\text {OUT}}$ </tex-math></inline-formula> voltage drop during the load transition. Because the SCLDO utilizes capacitor components when charging and discharging <inline-formula> <tex-math notation="LaTeX">$C_{\text {C}}$ </tex-math></inline-formula>, it provides robustness to process and temperature variations even at low-<inline-formula> <tex-math notation="LaTeX">$V_{\text {IN}}$ </tex-math></inline-formula> conditions. Therefore, the proposed time-based SCLDO achieved a <inline-formula> <tex-math notation="LaTeX">$V_{\text {OUT}}$ </tex-math></inline-formula> settling time of 4.4 ns at <inline-formula> <tex-math notation="LaTeX">$V_{\text {IN}}$ </tex-math></inline-formula> = 1 V and 13 ns at <inline-formula> <tex-math notation="LaTeX">$V_{\text {IN}}$ </tex-math></inline-formula> = 0.5 V condition. Fabricated in a 28-nm CMOS process, the proposed time-based SCLDO achieves a maximum <inline-formula> <tex-math notation="LaTeX">$I_{\text {OUT}}$ </tex-math></inline-formula> of 400 mA and a figure of merit (FoM) of 3.0 fs, with an active area of 0.021 mm2.
Details
- Language :
- English
- ISSN :
- 00189200 and 1558173X
- Volume :
- 59
- Issue :
- 2
- Database :
- Supplemental Index
- Journal :
- IEEE Journal of Solid-State Circuits
- Publication Type :
- Periodical
- Accession number :
- ejs65360670
- Full Text :
- https://doi.org/10.1109/JSSC.2023.3297605