Optimised architectures of Midori block cipher for area-constrained IoT applications

Over the past few years, lightweight cryptography has been recognised as top-notch for gratifying the requirements of resource-constrained environments (RCE) for Internet of Things (IoT) applications. For several RCE applications, a range of light-weight cryptographic methods have been put forth. In this paper, the Midori lightweight block cipher has been area optimised using unconventional serial architectures and memory address scheduling techniques. This paper suggests two serial architectures for area optimisation of 64-bit and 128-bit block sizes, respectively. The proposed designs are implemented in verilog hardware description language (HDL) using the Xilinx ISE Design suite. A fair comparison of the proposed designs has been done on different families of field programmable gate array (FPGA). The proposed design has shown a percentage improvement of 22.03% and 15.28% in terms of area for 64-bit and 128-bit block size, respectively. Similarly, the percentage improvement for throughput is 21.43% and 15.65% for 64-bit and 128-bit block size, respectively on FPGA Virtex-5 platform.