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A D-T Hybrid DC FCL and Its Parameter Optimization Design Method for Application in Multiterminal VSC-HVDC Grids

Authors :
He, Jiawei
Xue, Lei
Li, Bin
Xu, Lingling
Zhang, Guohua
Liu, Xinyang
Zhao, Xibei
Xu, Jianzhong
Source :
IEEE Transactions on Power Electronics; October 2024, Vol. 39 Issue: 10 p12867-12882, 16p
Publication Year :
2024

Abstract

It is important to limit the dc fault current in voltage source converter-based high-voltage direct-current (VSC-HVDC) grids for fault ride-through and safe operation. At present, the most typical method of fault current limitation in VSC-HVDC grids is to install dc reactors directly in the system. However, this will lead to a drastic increase in the required capacity of the direct current circuit breaker (DCCB) metal oxide varistor (MOV), increasing the manufacturing difficulty of the DCCB and reducing its operation reliability. Meanwhile, the dc fault current clearing time is also markedly prolonged, meaning that the dc fault handling speed is reduced. To solve above problems, several dc fault current limiters (FCLs) based on controlled (full-controlled or half-controlled) power electronic switches have been proposed, which inevitably incur a high cost. In this article, a novel diode–thyristor hybrid dc FCL is proposed. It can effectively reduce the high requirement on DCCB MOV rated capacity imposed by the dc reactor and increase the dc fault current clearing speed. In addition, compared with existing dc FCLs with similar functions, its cost is much lower due to the hybrid design. Furthermore, when applied to multiterminal VSC-HVDC grids, an accurate parameter design method for dc FCLs is innovatively proposed based on the concept of optimization. Finally, simulation case studies and experimental tests are carried out to prove the feasibility and superiority of the proposed method.

Details

Language :
English
ISSN :
08858993
Volume :
39
Issue :
10
Database :
Supplemental Index
Journal :
IEEE Transactions on Power Electronics
Publication Type :
Periodical
Accession number :
ejs67340275
Full Text :
https://doi.org/10.1109/TPEL.2024.3425600