Extended analysis of the Z²-FET: operation as capacitorless eDRAM

The Z²-FET operation as capacitorless DRAM\ud is analyzed using advanced 2-D TCAD simulations for IoT\ud applications. The simulated architecture is built based on\ud actual 28-nm fully depleted silicon-on-insulatordevices. It is\ud found that the triggering mechanism is dominated by the\ud front-gate bias and the carrier’s diffusion length. As in other\ud FB-DRAMs, the memory window is defined by the ON voltage\ud shift with the stored body charge. However, the Z²-FET’s\ud memory state is not exclusively defined by the inner charge\ud but also by the reading conditions.