Cite
Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State
MLA
Aziza, Hassan, et al. Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State. Sept. 2021. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.dedup.wf.001..7dee8f37ca6eee34b96ea4829e7f76ad&authtype=sso&custid=ns315887.
APA
Aziza, H., Hamdioui, S., Fieback, M., Taouil, M., Moreau, M., Girard, P., Virazel, A., & Coulié, K. (2021). Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State.
Chicago
Aziza, Hassan, Said Hamdioui, Moritz Fieback, Mottaqiallah Taouil, Mathieu Moreau, Patrick Girard, Arnaud Virazel, and K. Coulié. 2021. “Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State,” September. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.dedup.wf.001..7dee8f37ca6eee34b96ea4829e7f76ad&authtype=sso&custid=ns315887.