Low-Cost Energy-Efficient 3-D Nano-Spikes-Based Electric Cell Lysis Chips

Electric cell lysis (ECL) is a promising technique to be integrated with portable lab-on-a-chip without lysing agent due to its simplicity and fast processing. ECL is usually limited by the requirements of high power/voltage and costly fabrication. In this paper, we present low-cost 3-D nano-spikes-based ECL (NSP-ECL) chips for efficient cell lysis at low power consumption. Highly ordered High-Aspect-Ratio (HAR). NSP arrays with controllable dimensions were fabricated on commercial aluminum foils through scalable and electrochemical anodization and etching. The optimized multiple pulse protocols with minimized undesirable electrochemical reactions (gas and bubble generation), common on micro parallel-plate ECL chips. Due to the scalability of fabrication process, 3-D NSPs were fabricated on small chips as well as on 4-in wafers. Phase diagram was constructed by defining critical electric field to induce cell lysis and for cell lysis saturation $\text{E}_{sat}$ to define non-ECL and ECL regions for different pulse parameters. NSP-ECL chips have achieved excellent cell lysis efficiencies $\eta _{lysis}$ (ca 100%) at low applied voltages (2 V), 2~3 orders of magnitude lower than that of conventional systems. The energy consumption of NSP-ECL chips was 0.5–2 mJ/mL, 3~9 orders of magnitude lower as compared with the other methods (5J/mL-540kJ/mL).