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Investigation on High Aspect Ratio Multi-level Contact Holes Etching Process in Three-Dimensional Flash Memory Manufacturing

Authors :
Wen-jie Zhang
Bao-you Chen
Yu-qi Wang
Chuanbin Zeng
Liu Lipeng
Source :
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
Publication Year :
2018
Publisher :
IEEE, 2018.

Abstract

In the three-dimensional flash memory manufacturing technology, the etching process of high aspect ratio multi-level contact holes structure was studied. Using capacitive coupled plasma (CCP) etching equipment, the effects of C 4 F 6/ /C 4 F 8 /O 2 /Ar mixed gas atmosphere on the deep holes’ total profile were investigated to optimize bowing profile of the hole. Furthermore, multi-level stop layer loss was optimized by adjusting over etching time and lithography exposure critical dimension (CD), which proved good compatibility with existing process. Results show that adding proper amount of C 4 F 8 into C 4 F 6 gas atmosphere can achieve better verticality and less stop layer loss. Enlarging middle layer exposure CD can reduce specific stop layer loss independently while reducing over etching time can reduce all stop layer loss together. Under the optimized process parameters, the multi-level contact holes with aspect ratio range from 2.5/1 to 30/1 on staircase can be achieved at one etching time, and each stop layer loss is less than 50%.

Details

Database :
OpenAIRE
Journal :
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
Accession number :
edsair.doi...........069989daba14aa002e23274654f8d1ee