Extremely Scaled Si and Ge to L g = 3-nm FinFETs and L g = 1-nm Ultra-Thin Body Junctionless FET Simulation

Huge efforts are put into CMOS scaling to push the limits of Moore’s law. Semiconductor ICs manufacturing companies are currently ramping up 16-nm/14-nm FinFET processes, with 7 and 5 nm just around the corner.