A Real-Time Low-Power Coding Bit-Rate Control Scheme for High-Efficiency Video Coding in a Multiprocessor System-on-Chip

A real-time high-performance transmission bandwidth-aware (TB-aware) coding bit-rate (CBR) controller design with low power consumption and low hardware complexity is presented in this article for H.265/high-efficiency video coding (HEVC) in a multiprocessor system-on-chip (MPSoC). Previous TB-aware motion estimation designs with CBR-control capability in video coding have focused on algorithm development with precise CBR models, which require a complicated algorithmic derivation according to the system on-demand CBR and are difficult to realize in very large scale integration (VLSI) due to their lack of consideration for hardware implementation and modeling. Consequently, we present a hardware-oriented CBR-control algorithm that uses simple CBR control functions instead of requiring root and exponential operations to realize the real-time low-power design objective for HEVC applications within a mobile MPSoC. Then, an adequate hardware architecture with low hardware complexity is exploited to accomplish a low-power and high-speed VLSI design of a CBR controller for our proposed algorithm. Using diverse video-sized sequences under on-demand system coding-bit-rate constraints, the experimental outcomes demonstrate that the introduced design is capable of low power consumption and high speeds and can utilize low-complexity hardware.