Package Design Optimization for Intel SoC Xeon-D

Xeon-D brings the high performance of Xeon processors into a dense, low-power system-on-chip. This paper addresses the importance of cost–performance tradeoff analysis for the Xeon-D package. It describes how to determine the low-cost package factors (size, footprint, pin map, and layer count) without compromising the performance of the system. The 10-GbE signal integrity design and high-speed differential cost-performance optimization are discussed. Low-power architecture and package power delivery features including fully integrated voltage regulator are presented in this paper as well.