Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults

In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. A synthesis procedure for this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators. The experiment result shows that compared with the non-configurable 2-D LFSR, the average number of flip-flops is reduced by 79% for five benchmark circuits. The average number of faults detected by the configurable 2-D LFSR is 9.27% higher than that of the conventional LFSR and 0.57% higher than that of the non-configurable 2-D LFSR.