Cite
IR thermography and FEM simulation analysis of on-chip temperature during thermal-cycling power-metal reliability testing using in situ heated structures
MLA
Vladimír Košel, et al. “IR Thermography and FEM Simulation Analysis of On-Chip Temperature during Thermal-Cycling Power-Metal Reliability Testing Using in Situ Heated Structures.” Microelectronics Reliability, vol. 49, Sept. 2009, pp. 1132–36. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........0d16135d05b000ab823ff1b5d1896db6&authtype=sso&custid=ns315887.
APA
Vladimír Košel, Helmut Kock, Christian Djelassi, Michael Glavanovics, & Dionyz Pogany. (2009). IR thermography and FEM simulation analysis of on-chip temperature during thermal-cycling power-metal reliability testing using in situ heated structures. Microelectronics Reliability, 49, 1132–1136.
Chicago
Vladimír Košel, Helmut Kock, Christian Djelassi, Michael Glavanovics, and Dionyz Pogany. 2009. “IR Thermography and FEM Simulation Analysis of On-Chip Temperature during Thermal-Cycling Power-Metal Reliability Testing Using in Situ Heated Structures.” Microelectronics Reliability 49 (September): 1132–36. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........0d16135d05b000ab823ff1b5d1896db6&authtype=sso&custid=ns315887.