A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS

MLA

Daewoong Lee, et al. “A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 Nm CMOS.” 2019 Symposium on VLSI Circuits, June 2019. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........0f672b4fb2618006c668cea30759aea1&authtype=sso&custid=ns315887.

APA

Daewoong Lee, Yong-Hun Kim, Lee-Sup Kim, & Dongil Lee. (2019). A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS. 2019 Symposium on VLSI Circuits.

Chicago

Daewoong Lee, Yong-Hun Kim, Lee-Sup Kim, and Dongil Lee. 2019. “A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 Nm CMOS.” 2019 Symposium on VLSI Circuits, June. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........0f672b4fb2618006c668cea30759aea1&authtype=sso&custid=ns315887.