Memory Controller for 1Gb LPDDR2 Memory Initialization Sequence

MLA

Jin-Su Kang, et al. “Memory Controller for 1Gb LPDDR2 Memory Initialization Sequence.” The Journal of Korean Institute of Information Technology, vol. 20, Sept. 2022, pp. 63–71. EBSCOhost, https://doi.org/10.14801/jkiit.2022.20.9.63.

APA

Jin-Su Kang, Chang-Yong Lee, & Yong-Hwan Lee. (2022). Memory Controller for 1Gb LPDDR2 Memory Initialization Sequence. The Journal of Korean Institute of Information Technology, 20, 63–71. https://doi.org/10.14801/jkiit.2022.20.9.63

Chicago

Jin-Su Kang, Chang-Yong Lee, and Yong-Hwan Lee. 2022. “Memory Controller for 1Gb LPDDR2 Memory Initialization Sequence.” The Journal of Korean Institute of Information Technology 20 (September): 63–71. doi:10.14801/jkiit.2022.20.9.63.