Design of high‐speed gate driver to reduce switching loss and mitigate parasitic effects for SiC MOSFET

The high switching speed in a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) will aggravate the parasitic effects (d i /d t and d v /d t ) arising from the interaction with parasitic elements. In this project, a high-speed gate driver has been developed and optimised for the commercially available SiC MOSFET power module. The impact of various parasitic parameters on parasitic effects is initially evaluated. Then, an improved gate-assisted circuit is proposed with a local low-impedance path for both discharging and C d v/ d t currents. It allows maximised turn-off speed (d v /d t up to 36 V/ns) and minimised turn-off loss (reduction up to 70%). It also produces a reduction in electromagnetic interference. The gate voltage spike due to C d v/ d t current is reduced below the threshold voltage at various testing conditions.