Multiplier-free Realization of High Throughout Transpose Form FIR Filter

This paper presents a multiplier-free realization of the block finite impulse response (FIR) filter in transpose form configuration using binary constant shifts method (BCSM). The proposed architecture is synthesized using Xilinx Vivado and Cadence RTL Encounter compiler for the area and power analysis and is compared with the existing works in the literature. The comparison highlights the advantages of the proposed architecture in terms of power, hardware complexity and throughput for realizing reconfigurable high throughput block FIR filters.