Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits

Rapid single-flux-quantum (RSFQ) circuits are developing rapidly, but there are still many layouts that need to be completed manually, greatly reducing the design efficiency. We report the shape constraints of Josephson transmission line (JTL), and then propose automatic placement and routing methods for RSFQ circuits. First, for the pipeline structure of concurrent-flow clocking, a detailed placement algorithm based on simulated annealing is proposed, which use D Flip-Flop (DFF) insertion, column placement, and intra-column perturbation strategies to ensure the synchronization of clock phase while completing the placement of logic cells. More importantly, for the shape constraints of JTL, a new two-step JTL routing method is proposed. The first step is dummy wire routing, and the shape violations and routing congestion caused by shape constraints are solved to search legal paths for JTL routing; in the second step, timing optimization is performed when replacing dummy wire with JTL cells. Experimental results show that the proposed automatic methods achieve a 5% area-reduction and a 20× speed-up compared to manual design.