Computer Sub-Systems on a Chip of Silicon

This paper deals with current research aimed toward increasing circuit switching speed and logical complexity over that which is presently available on a given surface area of a silicon die. The relationship between circuit speed and power consumption is discussed for current mode logic circuitry. The technological tools available for pushing forward the barriers limiting speed and efficiency are presented. In addition, experimental data is shown comparing performance “of buried layer” devices to conventional devices in a ring oscillator configuration. Means for increasing logic complexity on a silicon die are discussed. A two phase shift bit example, developed and fabricated over a year ago, utilizing silicon interconnection cross-overs, is compared to a recent attempt utilizing film cross-overs. Also, results of integrating a 2×2 scratchpad memory device utilizing 101 elements are discussed. The paper concludes with some remarks pertaining to possible future technological approaches and their limitations for increasing logic complexity and circuit performance on a single chip of silicon.