Design of a 16 kbit superconducting latching/SFQ hybrid RAM

We have designed a 16 kbit superconducting latching/SFQ hybrid (SLASH) RAM, which enables high-frequency clock operation up to 10 GHz. The 16 kbit SLASH RAM consists of four 4 × 4 matrix arrays of 256 bit RAM blocks, block decoders, latching block drivers, latching block senses, impedance matched lines and the powering circuits. The 256 bit RAM block is composed of a 16 × 16 matrix array of vortex transitional memory cells, latching drivers, SFQ NOR decoders and latching sense circuits. We have also designed and implemented an SFQ NOR decoder that is composed of magnetically coupled multi-input OR gates and RSFQ inverters.