An FPGA-Based Hardware Accelerator for 2D Labeling

The 2D Labeling algorithm is used in many applications due to its superior image processing quality. As the requirements of image processing continue to increase, generating huge computational workloads, the efficient real-time implementation of this algorithm is very challenging. In recent years, research on accelerating 2D Labeling algorithms on GPUs has made rapid progress. However, GPU devices usually bring a large amount of energy consumption and are therefore not suitable for a wide range of applications in embedded scenarios. In this paper, we propose a highly integrated general-purpose hardware accelerator for medical image processing to effectively improve the computational performance of 2D Labeling algorithms and reduce the power consumption of FPGA devices. The design integrates image denoising, edge detection, and image segmentation algorithms in a hardware IP core based on a deep pipelining framework, which can effectively improve the speed of 2D Labeling algorithm during intensive medical image processing through parallel computing and data reuse. The design is implemented on Xilinx ZYNQ XC7Z020, and we consume very less energy and improve the computational performance by 1.3 and 2.1 times, respectively, compared to the software design based on advanced NVIDIA GeForce GTX 1660 Super and Intel(R) Core (TM) i7-10700 CPUs.