Nonlinear stored charge vs d.c. bias-current relationship under high-level injection in pin diodes

The i-region carrer lifetime in p-i-n diodes is frequently measured at a single bias current and the results extrapolated to higher or lower currents. This interpretation is erroneous, however, since high levels of d.c. bias injection can degrade the effective lifetime as seen at the device terminals. This paper shows the dependence of stored charge and carrier lifetime with d.c. bias current and device geometry. Experimental data are used to verify the analysis, which shows that this d.c. bias current dependence of the lifetime may be minimized by minimizing the low level injection carrier lifetime to i-region thickness ratio for a given device area.