Current starved delay element with symmetric load

Variable delay elements are often used in different types of high-speed integrated circuits, mainly intended for delay compensation, skew equalization, etc. These circuits are normally realized as hybrid, composed of digital and analog controlled parts. The digital part is used for coarse-grain, while the analog for fine-grain delay variation. Efficient analog delay element architecture is proposed in this paper. The proposal is based on modification of the standard current starved delay element solution. An analytical equation that corresponds to the delay of the circuit is given also. In terms of control voltage, the proposed circuit has a linear delay transfer function in the whole range of regulation. Improvement is achieved at a cost of small hardware overhead in respect to the standard solution. Delay linearity error is less than 1% and the agreement between analytical model and simulation results is good, i.e. the error is less than 5%.