An Input Insensitive Quantization Error Extraction Circuit for 8-MHz-BW 79-dB-DR CT MASH Delta–Sigma ADC With Multi-rate LMS-Based Background Calibration

This letter presents a continuous-time (CT) multi-stage noise-shaping (MASH) delta–sigma ADC with enhanced tolerance to temperature and operating frequency variations through multi-rate background calibration based on the least-mean-square (LMS) algorithm. A first stage modulator of the proposed ADC, which considers sufficient quantizer delay and reduces input signal leakage into second stage modulator, enables undisturbed quantization error cancellation with digital noise-cancellation filter (DNCF) calibration. A CT 2-2 MASH delta–sigma ADC prototype fabricated in 40-nm CMOS achieves DR of 79 dB, SNDR of 78.5 dB over an 8-MHz bandwidth, Schreier figure of merit (FoMs) of 168.9 dB and demonstrates conversion accuracy robustness within 1-dB SNDR fluctuation for temperature variations from −40 to 125 degrees, and within 2-dB SNDR degradation for frequency variation of 20% range.