Low noise accelerometer microsystem with highly configurable capacitive interface

This paper presents a low noise accelerometer microsystem with a highly configurable capacitive interface circuit. A programmable capacitive readout circuit is designed to minimize the offset and gain error due to the parasitic capacitance mismatch and the process variations. The interface circuit is implemented in a 0.5 μm 2P3M CMOS technology with EEPROM. The interface circuit and MEMS sensing element are integrated in a single package, and consist the accelerometer microsystem. The supply voltage and supply current of the system are 5 V and 1.17 mA, respectively. The input range and gain are 2.5 V and 0.5 V/g, respectively. The max---min gain error and max---min offset error after calibration was measured to be 1.2% FSO and 3.3% FSO, respectively. The signal to noise ratio (SNR) and noise equivalent resolution (NER) are measured to be 93.1 dB and 110.6 μg/?Hz, respectively, when a 40 Hz, 5 g sinusoidal input acceleration is applied.