Topology-Aided Multicorner Timing Predictor for Wide Voltage Design

Wide voltage design has been widely used to achieve power reduction and energy efficiency improvement. The consequent increasing number of PVT corners poses severe challenges to timing analysis in terms of accuracy and efficiency, especially for low voltage corners. In this paper, a learning-based timing prediction framework is proposed to predict multi-corner path delays across wide voltage range by exploiting both the correlations of circuit topology information and timing analysis results from known corners, which are respectively captured by LSTM (Long Short-Term Memory) and MMoE (Multi-gate Mixture-of-Experts) networks. Experimental results demonstrate that with the proposed framework, the path delays at low voltages could be predicted across wide voltage range with rRMSE of less than 2.9% and 4.7% for seen and unseen circuits respectively. Compared with the learning-based models used in prior works, the proposed framework achieves significant prediction error reduction by up to 19.1×.