Characteristics of Recessed-Gate TFETs With Line Tunneling

In this paper, we propose a recessed-gate tunneling field-effect transistor (TFET) to improve the on current of TFETs by increasing the tunnel area with line tunneling. We investigate the effects of the recessed-body thickness and the doping level on the device performance. For optimal device structures, our proposed n-TFET reaches $1.44 \times 10^{-6}$ A/ $\mu \text{m}$ of on current and $3.22 \times 10^{9}$ ON/ OFF current ratio. A minimum subthreshold swing SS $_{{\textsf {min}}} = 28.3$ mV/dec and an average swing SS $_{{\textsf {avg}}} = 59.8$ mV/dec over seven orders of drain current are achieved. In addition, complementary TFET inverters show good noise margins of $\textsf {NM}_{H} = 65$ mV (38.5 % $V_{{\textsf {DD}}}$ ) and NM $_{L} = 77$ mV (32.5 % $V_{{\textsf {DD}}}$ ) and also a high voltage gain even at $V_{{\textsf {DD}}} = 0.2$ V.