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Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors
- Source :
- Computer Architecture ISBN: 9783642243219, ISCA Workshops
- Publication Year :
- 2011
- Publisher :
- Springer Berlin Heidelberg, 2011.
-
Abstract
- In this work we introduce power optimizations relying on partial tag comparison (PTC) in snoop-based chip multiprocessors. Our optimizations rely on the observation that detecting tag mismatches in a snoop-based chip multiprocessor does not require aggressively processing the entire tag. In fact, a high percentage of cache mismatches could be detected by utilizing a small subset but highly informative portion of the tag bits.Based on this, we introduce a source-based snoop filtering mechanism referred to as S-PTC. In S-PTC possible remote tag mismatches are detected prior to sending the request. We reduce power as S-PTC prevents sending unnecessary snoops and avoids unessential tag lookups at the end-points. Furthermore, S-PTC improves performance as a result of early cache miss detection.S-PTC improves average performance from 2.9% to 3.5% for different configurations and for the SPLASH-2 benchmarks used in this study. Our solutions reduce snoop request bandwidth from 78.5% to 81.9% and average tag array dynamic power by about 52%.
Details
- ISBN :
- 978-3-642-24321-9
- ISBNs :
- 9783642243219
- Database :
- OpenAIRE
- Journal :
- Computer Architecture ISBN: 9783642243219, ISCA Workshops
- Accession number :
- edsair.doi...........396262b60eff4930700af8f0178fcbe4
- Full Text :
- https://doi.org/10.1007/978-3-642-24322-6_18