Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.