Configurable,Highly Parallel (CHiP) Approach For Signal Processing Applications

Between the conception of a real time signal processor and its functional, VLSI realization there is an enormous amount of effort devoted to designing, revising, optimizing and testing. Since the process is cumulative -- later work builds on previous work -- and since the activity becomes progressively more detailed, more constrained and more exacting, it follows that the global design parameters should be fully explored. Global design decisions, when correct, can have a greater effect on performance than many local optimiza-tions. When the decisions are wrong, they can cause continual difficulty. Accordingly, we propose a design methodology based on the Configurable, Highly Parallel (CHiP) architecture family1 that focuses on exploring global design parameters and is especially well suited to the VLSI implementation of signal processing systems.