Cu/barrier CMP on porous low-k based interconnect schemes

Dielectric stacks containing porous low-k materials were investigated regarding their ability to pass CMP processes as used in Cu interconnect technology. Beside the low-k material itself, the impact of layout, cap layer materials and different diffusion barrier materials has been proven. Advanced consumables, partly specially designed for future technology nodes, have been tested within these experiments. Compatibility of the slurries with the low-k stacks, dishing and erosion, impact of polishing parameters like down force and platen speed on low-k stack integrity were examined. Low-k stacks based on a porous MSQ material capped with PECVD-SiC or with a MSQ-hard mask were found to be promising candidates. Low-k stacks based on porous SiO"2-aerogel could not meet the stability requirements at present and need additional efforts for adhesion enhancement between cap layer and porous material. Consumables used within the experiments enable an efficient processing with low dishing and erosion as well as an excellent surface quality.