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IDeF-X ECLAIRs: An ultra low noise CMOS ASIC for the readout of Cd(Zn)Te detectors
- Source :
- 2007 IEEE Nuclear Science Symposium Conference Record.
- Publication Year :
- 2007
- Publisher :
- IEEE, 2007.
-
Abstract
- The very last member of the IDeF-X ASIC family is presented: IDeF-X ECLAIRs is a 32-channel front end ASIC designed for the readout of low capacitive (2 to 5 pF) and low leakage current (1 pA to 2 nA) cadmium telluride (CdTe) and cadmium zinc telluride detectors (CdZnTe). Thanks to its ultra low noise performances (equivalent noise charge floor of 33 e- rms) and to its radiation hardened design (single event latchup linear energy transfer threshold of 56 MeV.cm2.mg-1), the chip is well suited for very low energy discrimination, very high energy resolution, "space proof," hard X-ray spectroscopy. We measured a very low energy threshold of less than 2 keV with a 14 pF input capacitor and a minimal sensitivity of the equivalent noise charge (ENC) to input capacitance of less than 7 e-/pF obtained with a 6 mus peaking time. IDeF-X ECLAIRs will be used for the readout of 6400 CdTe Schottky monopixel detectors of the 2D coded mask imaging telescope ECLAIRs aboard the SVOM satellite [1]. IDeF-X ECLAIRs has also been designed for the readout of a pixelated CdTe detector in the future miniature spectro-imager prototype CALISTE 256 that is currently foreseen for the high energy detector module of the SIMBOL-X mission [2], [3].
Details
- ISSN :
- 10823654
- Database :
- OpenAIRE
- Journal :
- 2007 IEEE Nuclear Science Symposium Conference Record
- Accession number :
- edsair.doi...........4079057951ae37b5c10a79c40942c344
- Full Text :
- https://doi.org/10.1109/nssmic.2007.4436341