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Towards high performance network-on-chip: A survey on enabling technologies, open issues and challenges

Authors :
Ng Yen Phing
R. Badlishah Ahmad
Fazrul Faiz Zakaria
Phaklen Ehkan
F. W. Zulkefli
Mohd Nazri Mohd Warip
Source :
2016 3rd International Conference on Electronic Design (ICED).
Publication Year :
2016
Publisher :
IEEE, 2016.

Abstract

One of the greatest challenges with cutting edge technology in System-on-Chip (SoC) is capability of processing core especially for complex and larger network size interconnections. Additionally, it is important to consider the effectiveness of routing algorithm in the overall performance of Network-on-Chip (NoC). Hence, the design and implementation of networks-on-chip should be considering aspects of simplicity in design, bandwidth usage, delay and power consumption. In essence, adaptive technique is a potential routing algorithm for better performance in network-on-chip (NoC) in which have properties such as prevention of livelock, deadlock, and starvation. This paper employed survey to investigate the impact of deterministic routing algorithm that has degrade overall performance and deadlock happen due to the fixed direction to the destination. An adaptive routing algorithm straighten out the problem of deadlock from deterministic routing algorithm by providing routing flexibility.

Details

Database :
OpenAIRE
Journal :
2016 3rd International Conference on Electronic Design (ICED)
Accession number :
edsair.doi...........41071273c761f168c3dc136805b2151e