Challenge of MOS/MTJ-hybrid nonvolatile logic-in-memory architecture in dark-silicon era

In this paper, we present a new architecture-level approach, called “nonvolatile logic-in-memory (NV-LIM) architecture,” to solving performance-wall and power-wall problems due to the present CMOS-only-based logic-LSI processors [1]. Figure 1(a) shows a conventional logic LSI chip architecture, where global interconnections between logic and volatile memory modules dominates performance and power dissipation as well as leakage power continuously consumed by volatile memories. In contrast, since nonvolatile storage elements such as magnetic tunnel junction (MTJ) devices are easily distributed over a logic-circuit plane by using a 3D stack structure as shown in Figure 1(b), performance degradation due to intra-chip global wires can be drastically mitigated, which leads to a high- performance, ultra-low-power and highly reliable (or highly resilient) logic LSI.