6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links

A recent trend in high-performance systems is distribution of computing across many chips and packages to sustain performance scaling while achieving high yield and alleviating power delivery. High-end data center systems and new applications like deep neural network (DNN) accelerators with scalable architecture [1] may extend the system from large chip-scale computing not just to package-scale multi-chip modules (MCM), but also to PCB-scale computing systems. An essential requirement for these distributed systems is a highly scalable low-power and high-bandwidth interconnect system, that can cover a wide range of integration and channel distances. Ideally, the same low-power links designed for ultra-short reach interconnects in MCM should be used in more challenging board-level environments.