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Modeling Process Variability in Scaled CMOS Technology
- Source :
- IEEE Design & Test of Computers. 27:8-16
- Publication Year :
- 2010
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2010.
-
Abstract
- Process variability has become a critical issue in scaled CMOS design. This article provides a comprehensive view on the predominant variation sources in sub-90-nm devices, their impact on device and circuit performance, and various modeling approaches for statistical circuit analysis.
Details
- ISSN :
- 07407475
- Volume :
- 27
- Database :
- OpenAIRE
- Journal :
- IEEE Design & Test of Computers
- Accession number :
- edsair.doi...........475121f5f273893c9db5010d62422f05