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Self-Aligned-Gate ZnO TFT Circuits
- Source :
- IEEE Electron Device Letters. 31:326-328
- Publication Year :
- 2010
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2010.
-
Abstract
- We report combining plasma-enhanced atomic layer deposition (PEALD) ZnO thin-film transistors (TFTs) with a gate-self-aligned process to fabricate high-speed circuits. The speed of our previous PEALD circuits (22 ns/stage) was largely limited by the parasitic capacitance between the gate and drain, and a selfaligned-gate process provides higher speed devices and circuits. In this letter, a backside exposure process was used to fabricate gate-self-aligned TFTs with a mobility of 20 cm2/V · s. The seven-stage self-aligned-gate PEALD ZnO TFT ring oscillators had a propagation delay of 9.8 ns/stage at a supply voltage of 18 V. These ring oscillators are similar in performance to the best reported saturated-load oxide-semiconductor circuits but with much longer channel length (> 5× longer).
- Subjects :
- Materials science
business.industry
Transistor
Electrical engineering
Propagation delay
Ring oscillator
Self-aligned gate
Capacitance
Electronic, Optical and Magnetic Materials
law.invention
Atomic layer deposition
Parasitic capacitance
law
Thin-film transistor
Optoelectronics
Electrical and Electronic Engineering
business
Subjects
Details
- ISSN :
- 15580563 and 07413106
- Volume :
- 31
- Database :
- OpenAIRE
- Journal :
- IEEE Electron Device Letters
- Accession number :
- edsair.doi...........47a6a5219decfc22e54ac019e01408d1