Functional units utilization in a multiple-instruction issue architecture

We present a study regarding functional unit utilization in a multiple instruction issue machine: a VLIW processor supporting the conditional execution concept. Since all the instructions are conditionally executed, then we can have several instruction scheduling alternatives to fill the fields of the very large instructions. For example, we can have instructions proceeding from different basic blocks sharing the same very large instructions. The paper shows some instruction scheduling schemes, and how they affect the degree of the occupation of the functional units of machine configurations derived from the basic model of conditional execution architecture.