An FPGA Based Control Algorithm for Cascaded Multilevel Inverters

In recent years, thanks to the various developments in VLSI, Field-Programmable Gate Arrays (FPGAs) have become key components in implementing high performance digital signal processing (DSP) systems, especially in the areas of digital communications, networking, video and imaging but its potential is not fully utilized in the area of power control and conversions. The logic fabric of today's FPGAs consists not only of look-up tables, registers, multiplexers, distributed and block memory, but also dedicated circuitry for fast adders, multipliers, and I/O processing (e.g., giga-bit I/O). The memory bandwidth of a modern FPGA far exceeds that of a microprocessor or DSP processor running at clock rates two to ten times that of the FPGA. Coupled with a capability for implementing highly parallel arithmetic architectures, this makes the FPGA ideally suited for creating high-performance custom data path processors for tasks such as digital filtering, fast Fourier transforms, and forward error correction. In this paper a XILINX FPGA based multilevel PWM three phase inverter test rig was constructed by adding bi-directional switches to the conventional bridge topology and its performance is suitably analysed. The inverter can produce three and five different output voltage levels across the load. XILINX FPGA is a programmable logic device developed by XILINX which is considered as an efficient hardware for rapid prototyping. It is used as a SVPWM generator to apply the appropriate signals to inverter switches. In addition to XILINX FPGA, Matlab/Simulink, system Generator software was used for simulation and verification of the proposed circuit before implementation, Simulation and experimental results show that both are in close agreement. The present PWM signal generation scheme can be used for any multilevel inverter configuration with minimum changes in driver circuit.