Writing Efficient VHDL Descriptions

There are several ways of describing a design in VHDL which are functionally equivalent, yet are mapped to circuits of different sizes. Although certain transformation rules can be applied to optimize some “redundant descriptions”, it is generally a designer’s responsibility to develop a design description which will lead to an efficient circuit implementation. Take the following VHDL program as an example. TWO is declared as a signal in Process_A and a constant 2 is assigned to it. In Process_B, it is multiplied by signal B and the result is stored in signal C. Since TWO is assigned outside the process Mult_By_Two, the synthesizer may not able to recognize that TWO can be reduced to a constant. Thus, a regular multiplier will be synthesized to the assignment statement in Process_B. Fig. 13.1(a) shows a circuit using a regular multiplier for the operation.