Precision techniques for whole wafer dicing and thinning of superconducting mixer circuits

Present designs for millimeter and submillimeter superconducting mixer circuits often require finished quartz wafer thicknesses from a few mils to less than a mil. Typically this is accomplished by first dicing the wafer into individual chips and then thinning each chip separately. In our new process the entire wafer is first diced; however, the cuts are only made two mils deeper than the desired finished chip thickness. An ultra-flat Si wafer is prepared with a 5 /spl mu/m thick Apiezon-W black wax coating on both sides. The quartz wafer is mounted to the Si carrier, cuts side down, which is itself mounted to a stainless steel lapping block. The "stack" of block/Si/quartz is then placed in a tool designed to permit compression of the sandwich to 30 psi at 145C. In this process the quartz wafer is positioned flat with respect to the Si wafer to better than +/-2.5 /spl mu/m. The stack is then lapped and polished through the backside of the wafer, into the cuts to the desired wafer thickness to better than +/-5 /spl mu/m. The Si/quartz bilayer is subsequently removed from the block resulting in a fully diced and thinned quartz wafer.