Design of HV-CMOS Detectors in BCD Technology with Noise and Crosstalk Measurements

This paper presents the design and implementation of a particle detector in a Bipolar-CMOS-DMOS (BCD) 180 nm technology. The design has a substrate potential of — 50 V and supply voltage of 1.8 V. Size of the unit pixel sensor is $250\times 50\ \mu\mathbf{m}^{2}$ . The chip consists of an array of $47\times 6$ pixels including the signal processing circuitry. The total chip area is $3.3 \times 4.4\ \mathbf{mm}^{2}$ . The complete signal processing circuitry is hosted inside the diode sensor to achieve 100% fill factor. The chip consists of 106 input-output pads, including the pads for supplies viz. — 50 V, 0 V and 1.8 V. The measurement results are presented to validate the noise and crosstalk models of the designed detector. The comparison shows an average mismatch of 2.65 $\mu\mathbf{V}$ for the crosstalk voltages in a range of 3000 to 7000 injected electrons. The circuit noise has an average mismatch of $1.23\times 10^{-10}\ \mathbf{V}^{2}/\mathbf{Hz}$ between the analytical and the measurement results for a frequency range of 100 kHz to 22 MHz. The analog processing circuitry provides a measured voltage gain of 33.3 dB at 100 kHz of input frequency.