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A high-speed dual modulus prescaler using 0.25 µm CMOS Technology

Authors :
Wen-rong Yang
Jia-lin Cao
Feng Ran
Jian Wang
Source :
Journal of Shanghai University (English Edition). 8:342-347
Publication Year :
2004
Publisher :
Springer Science and Business Media LLC, 2004.

Abstract

A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 µm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 ; µm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.

Details

ISSN :
1863236X and 10076417
Volume :
8
Database :
OpenAIRE
Journal :
Journal of Shanghai University (English Edition)
Accession number :
edsair.doi...........5837741ec0cb447606b65bd6d3d81e1e