Design of DVB-S2 LDPC Coder and Decoder Implemented in FPGA

Full parallel architecture for DVB-S2 LDPC was implemented on the platform of FPGA, in this process, the pipeline technology was introduced, and the method of FIFO and multiple RAM group used at the same time was also used, the problem of storing the parity check matrix was effectively overcomed, and the coding rate reaches 125Mbps. In order to solve the problem of high consumption of resources, the design of decoder adopted serial architecture, the decoding delay was greatly reduced by clever design of interleaver structure, and the decoding throughput reaches 125Mbps, moreover utilization of registers and logic elements is less than 1%.