A Multiscale Simulation Framework for Steep-Slope Si Nanowire Cold Source FET

Source engineering is an emerging technique to achieve steep-slope switching FET. To bridge the new carrier filtering mechanism and device performance, a multiscale simulation framework is presented in this article and is applied in Si nanowire (NW) cold source FET (CSFET). By the fit-parameter-free density functional theory (DFT) method, the key component of cold source (CS) design for broken-gap-like band alignment and high cold carrier injection is demonstrated. The novel device switching mechanism is also verified in the entire device scale with fully quantum atomistic tight-binding (TB) and nonequilibrium Green’s function (NEGF) methods. Although these tools are physics-based and accurate, the device scale is limited, and the computation burden is heavy. Thus, half-empirical TCAD simulation is suitable for device design and path-finding in realistic geometry. Key components of the CS and energy filtering effect can be verified by DFT-NEGF and TB-NEGF methods. Based on TCAD results, we implement a circuit-level benchmark for early stage path-finding. The results show that gate-all-around (GAA) Si NW CSFET is a potential candidate for low-power application, which enables supply voltage scaling.